I. Field of the Disclosure
The field of the present disclosure relates to detecting bit flips in cache memory in processor-based systems.
II. Background
A memory cell is a basic building block of computer data storage, which is also known as “memory.” A computer system may either read data from or write data to memory. Memory can be used to provide cache memory in a central processing unit (CPU) system as an example. Cache memory is a smaller, faster memory that stores copies of data stored at frequently accessed memory addresses in main memory or higher level cache memory to reduce memory access latency. Thus, cache memory is memory that can be used by a CPU to reduce memory access times.
Cache memory is comprised of a tag array and a data array. The tag array contains addresses also known as “tags.” The tags provide indexes into data storage locations in the data array. A tag in the tag array and data stored at the index of the tag in the data array is also known as a “cache line” or “cache entry.” If a memory address, or portion thereof, provided to the cache memory as part of a memory access request matches a tag in the tag array, this is known as a “cache hit.” A cache hit means that the data in the data array contained at the index of the matching tag contains data corresponding to the requested memory address in main memory and/or a higher level cache memory. The data contained in the data array at the index of the matching tag can be used for the memory access request, as opposed to having to access main memory or a higher level cache memory having greater memory access latency. If however, the memory address of the memory access request, or portion thereof, does not match a tag in the tag array, or if the cache entry is otherwise invalid, this is known as a “cache miss.” In a cache miss, the data array is deemed not to contain data that can satisfy the memory access request.
For a cache hit, not only must a memory address, or portion thereof, of a memory access request match a tag in the tag array, the cache entry corresponding to the matched tag must also be valid. In this regard, a valid indicator (e.g., a valid bit) is provided for each cache entry in the cache memory to indicate the validity of the cache entry. Thus, the valid indicator is also consulted in a cache memory access as part of cache error logic. The valid indicator may be set to an invalid state when the data stored in the data array for the cache entry is no longer valid. The valid indicator also provides a convenient method for deleting a cache entry. To delete a cache entry, the valid indicator corresponding to the cache entry to be deleted can simply be set to an invalid state (e.g., a logical zero ‘0’ value, where a logical one ‘1’ value indicates a valid state), as opposed to overwriting the data stored in the data array for the cache entry. Thus, if a deleted cache entry is subsequently accessed before being filled with valid data, the valid indicator for the accessed cache entry will represent an invalid state for the cache entry. In this instance, the valid indicator will cause the cache memory to generate a cache miss for the cache entry access. However, if an unintentional bit flip occurs in the valid indicator thereby causing the valid indicator to improperly indicate a valid state for an invalid cache entry, such as from radiation or a power surge as examples, the cache memory will generate a false cache hit when accessing this invalid cache entry, as opposed to a true cache miss. As a result, invalid data may be provided from the cache memory for the memory access request as a result of the valid indicator bit flip.
Thus, it is desired in cache memory designs to account for the possibility of bit flips in valid indicators. One method to account for bit flips in the valid indicators in cache memory is to protect against bit flips from occurring. For example, the valid indicators can be radiation-hardened to make the valid indicators less susceptible to bit flips. However, radiation hardening may add cost or circuit complexity in a manner that decreases performance of cache memory.
An alternative method to protect against bit flips from occurring in valid indicators in cache memory is to detect bit flips in the valid indicators. One method of detecting bit flips in valid indicators is to duplicate the valid indicator in each cache entry in cache memory. The cache memory is designed to only generate a cache hit if both valid indicators for an accessed cache entry are valid. Thus, if a bit flip occurs in one of the valid indicators, the duplicate valid indicator will not match. However, duplicating valid indicators in cache entries in cache memory requires additional circuitry in the cache memory. Access latency to the cache memory and the energy consumed by the cache access may also be increased as a result of providing duplicated valid indicators for the additional logic required to determine if the valid indicators for an accessed cache entry match. Also, if the same bit flip occurs in duplicated valid indicators for a given cache entry, the valid indicators will still match and possibly generate a false cache hit.
Another method of detecting bit flips in valid indicators in cache memory is to include the valid indicators in a parity operation and parity check. Parity logic may be provided in cache memory to generate a parity (e.g., a parity bit or word) for a cache entry or portion thereof that includes a valid indicator for the cache entry on a fill of the cache entry. The parity is checked when a cache entry is accessed in the cache memory. If an unintended bit flip has occurred, the generated parity will not match the parity of the cache entry, or portion thereof, and a cache miss will be generated by the cache memory as a result. Thus, if the valid indicator of a cache entry is included in the generation of the parity, a bit flip in the valid indicator will result in a parity mismatch that will be used to generate a cache miss or to signal an error. However, providing a valid indicator as part of a parity indicator can be disadvantageous. If the valid indicator is included in the parity for the cache entry, the parity must be regenerated when a cache entry in the cache memory is changed. Thus, if a cache entry is deleted, the valid indicator cannot simply be set to an invalid state. A new parity indicator must also be generated and stored in the cache entry, thereby increasing latency and energy of a cache entry deletion operation. This performance penalty and increase in energy can be substantial if cache memory supports “flash invalidate” or “selective invalidate” operations that allow multiple cache entries in the cache memory to be invalidated simultaneously and quickly by simply invalidating the valid indicators. If the valid indicator of a cache memory is included in the parity for a cache entry, the parity for each invalidated cache entry must also be regenerated for each cache flash invalidate or selective invalidate operation.